1. Field of the Invention
The present invention relates to a method and apparatus for demodulating a square root. More particularly, the present invention relates to a method and apparatus used by a digital system or a signal communication system for demodulating a square root.
2. Description of the Related Art
In a very large scale integrated circuit (VLSI) digital system or a signal communication system, two input signals I and Q are often modulated into √{square root over (I2+Q2)}. In other words, the input values I and Q are combined to form a square root of the sum of squares. To obtain an accurate value of the square root, lots of hardware is required. Moreover, the performance of hardware is usually poor and the processing time is usually long. Hence, hardware circuits are not too suitable for the real-time computation of square roots. To resolve this problem, methods and apparatus for finding an approximate solution such as the coordinate rotation digital computer (CORDIC), the angular cone approximate wave envelop inspection method and circuits and so on have been developed.
In Taiwan Patent No. 480.415, a square root demodulation apparatus is disclosed. In the invention, a coordinate slicing theory is utilized to obtain an approximate square root of two input signals I and Q. Although the patent is capable of resolving the aforementioned problems, too many comparators must be used to obtain the solution. Therefore, the required integrated circuit is large and its production cost is high.
FIG. 1 is a table listing the relation between angle and error ratio for the aforementioned Taiwan Patent No. 480.415. As shown in FIG. 1, the error ratios within some range of phase angles (the ones inside the circles) for the input signals I and Q are large. For example, the error ration when the angle is 76° is as high as 3.00303%. This error ratio is quire significant in a communication system or other digital computation system having a narrow tolerance for errors.